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<a href="#define-members">Macros</a>  </div>
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<div class="title">xcsudma_hw.h File Reference</div>  </div>
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Macros</h2></td></tr>
<tr class="memitem:gaf7ae40275005f5b2c827da41a0e3cc23"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__csudma__v1__0.html#gaf7ae40275005f5b2c827da41a0e3cc23">XCSUDMA_HW_H_</a></td></tr>
<tr class="memdesc:gaf7ae40275005f5b2c827da41a0e3cc23"><td class="mdescLeft">&#160;</td><td class="mdescRight">Prevent circular inclusions by using protection macros.  <a href="group__csudma__v1__0.html#gaf7ae40275005f5b2c827da41a0e3cc23">More...</a><br /></td></tr>
<tr class="separator:gaf7ae40275005f5b2c827da41a0e3cc23"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gae02862bee946eeb9f0684d24550d1afa"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__csudma__v1__0.html#gae02862bee946eeb9f0684d24550d1afa">XCsuDma_In32</a>&#160;&#160;&#160;Xil_In32</td></tr>
<tr class="memdesc:gae02862bee946eeb9f0684d24550d1afa"><td class="mdescLeft">&#160;</td><td class="mdescRight">Input operation.  <a href="group__csudma__v1__0.html#gae02862bee946eeb9f0684d24550d1afa">More...</a><br /></td></tr>
<tr class="separator:gae02862bee946eeb9f0684d24550d1afa"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gae5b5c8718f050b6b4e25380a92c9aa0d"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__csudma__v1__0.html#gae5b5c8718f050b6b4e25380a92c9aa0d">XCsuDma_Out32</a>&#160;&#160;&#160;Xil_Out32</td></tr>
<tr class="memdesc:gae5b5c8718f050b6b4e25380a92c9aa0d"><td class="mdescLeft">&#160;</td><td class="mdescRight">Output operation.  <a href="group__csudma__v1__0.html#gae5b5c8718f050b6b4e25380a92c9aa0d">More...</a><br /></td></tr>
<tr class="separator:gae5b5c8718f050b6b4e25380a92c9aa0d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga356d29aa2d43a1b724700007be7dcd51"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__csudma__v1__0.html#ga356d29aa2d43a1b724700007be7dcd51">XCsuDma_ReadReg</a>(BaseAddress,  RegOffset)&#160;&#160;&#160;<a class="el" href="group__csudma__v1__0.html#gae02862bee946eeb9f0684d24550d1afa">XCsuDma_In32</a>((BaseAddress) + (u32)(RegOffset))</td></tr>
<tr class="memdesc:ga356d29aa2d43a1b724700007be7dcd51"><td class="mdescLeft">&#160;</td><td class="mdescRight">This macro reads the given register.  <a href="group__csudma__v1__0.html#ga356d29aa2d43a1b724700007be7dcd51">More...</a><br /></td></tr>
<tr class="separator:ga356d29aa2d43a1b724700007be7dcd51"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga5a2390fe93e02061d01c3b9e057b3b2b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__csudma__v1__0.html#ga5a2390fe93e02061d01c3b9e057b3b2b">XCsuDma_WriteReg</a>(BaseAddress,  RegOffset,  Data)&#160;&#160;&#160;<a class="el" href="group__csudma__v1__0.html#gae5b5c8718f050b6b4e25380a92c9aa0d">XCsuDma_Out32</a>((BaseAddress) + (u32)(RegOffset), (u32)(Data))</td></tr>
<tr class="memdesc:ga5a2390fe93e02061d01c3b9e057b3b2b"><td class="mdescLeft">&#160;</td><td class="mdescRight">This macro writes the value into the given register.  <a href="group__csudma__v1__0.html#ga5a2390fe93e02061d01c3b9e057b3b2b">More...</a><br /></td></tr>
<tr class="separator:ga5a2390fe93e02061d01c3b9e057b3b2b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Registers offsets</div></td></tr>
<tr class="memitem:ga76fcd0f2a0c7ebc2058f231a944c7109"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__csudma__v1__0.html#ga76fcd0f2a0c7ebc2058f231a944c7109">XCSUDMA_ADDR_OFFSET</a>&#160;&#160;&#160;0x000</td></tr>
<tr class="memdesc:ga76fcd0f2a0c7ebc2058f231a944c7109"><td class="mdescLeft">&#160;</td><td class="mdescRight">Address Register Offset.  <a href="group__csudma__v1__0.html#ga76fcd0f2a0c7ebc2058f231a944c7109">More...</a><br /></td></tr>
<tr class="separator:ga76fcd0f2a0c7ebc2058f231a944c7109"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaf5d3e01cba7a5d0029901f690007a9c0"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__csudma__v1__0.html#gaf5d3e01cba7a5d0029901f690007a9c0">XCSUDMA_SIZE_OFFSET</a>&#160;&#160;&#160;0x004</td></tr>
<tr class="memdesc:gaf5d3e01cba7a5d0029901f690007a9c0"><td class="mdescLeft">&#160;</td><td class="mdescRight">Size Register Offset.  <a href="group__csudma__v1__0.html#gaf5d3e01cba7a5d0029901f690007a9c0">More...</a><br /></td></tr>
<tr class="separator:gaf5d3e01cba7a5d0029901f690007a9c0"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaa69407558163d5fc58ac9621b3e313a3"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__csudma__v1__0.html#gaa69407558163d5fc58ac9621b3e313a3">XCSUDMA_STS_OFFSET</a>&#160;&#160;&#160;0x008</td></tr>
<tr class="memdesc:gaa69407558163d5fc58ac9621b3e313a3"><td class="mdescLeft">&#160;</td><td class="mdescRight">Status Register Offset.  <a href="group__csudma__v1__0.html#gaa69407558163d5fc58ac9621b3e313a3">More...</a><br /></td></tr>
<tr class="separator:gaa69407558163d5fc58ac9621b3e313a3"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga60d1ed5209af6a5d9e9c55b6b95052de"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__csudma__v1__0.html#ga60d1ed5209af6a5d9e9c55b6b95052de">XCSUDMA_CTRL_OFFSET</a>&#160;&#160;&#160;0x00C</td></tr>
<tr class="memdesc:ga60d1ed5209af6a5d9e9c55b6b95052de"><td class="mdescLeft">&#160;</td><td class="mdescRight">Control Register Offset.  <a href="group__csudma__v1__0.html#ga60d1ed5209af6a5d9e9c55b6b95052de">More...</a><br /></td></tr>
<tr class="separator:ga60d1ed5209af6a5d9e9c55b6b95052de"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga742012672c371578fc7fce4908f173f6"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__csudma__v1__0.html#ga742012672c371578fc7fce4908f173f6">XCSUDMA_CRC_OFFSET</a>&#160;&#160;&#160;0x010</td></tr>
<tr class="memdesc:ga742012672c371578fc7fce4908f173f6"><td class="mdescLeft">&#160;</td><td class="mdescRight">CheckSum Register Offset.  <a href="group__csudma__v1__0.html#ga742012672c371578fc7fce4908f173f6">More...</a><br /></td></tr>
<tr class="separator:ga742012672c371578fc7fce4908f173f6"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gab56adb100901bb2b042a842619064ce5"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__csudma__v1__0.html#gab56adb100901bb2b042a842619064ce5">XCSUDMA_I_STS_OFFSET</a>&#160;&#160;&#160;0x014</td></tr>
<tr class="memdesc:gab56adb100901bb2b042a842619064ce5"><td class="mdescLeft">&#160;</td><td class="mdescRight">Interrupt Status Register Offset.  <a href="group__csudma__v1__0.html#gab56adb100901bb2b042a842619064ce5">More...</a><br /></td></tr>
<tr class="separator:gab56adb100901bb2b042a842619064ce5"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga0f05af1a6ce895ebbd4bdb099ead152c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__csudma__v1__0.html#ga0f05af1a6ce895ebbd4bdb099ead152c">XCSUDMA_I_EN_OFFSET</a>&#160;&#160;&#160;0x018</td></tr>
<tr class="memdesc:ga0f05af1a6ce895ebbd4bdb099ead152c"><td class="mdescLeft">&#160;</td><td class="mdescRight">Interrupt Enable Register Offset.  <a href="group__csudma__v1__0.html#ga0f05af1a6ce895ebbd4bdb099ead152c">More...</a><br /></td></tr>
<tr class="separator:ga0f05af1a6ce895ebbd4bdb099ead152c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga302a6020f0d9a857d490320f4a20c873"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__csudma__v1__0.html#ga302a6020f0d9a857d490320f4a20c873">XCSUDMA_I_DIS_OFFSET</a>&#160;&#160;&#160;0x01C</td></tr>
<tr class="memdesc:ga302a6020f0d9a857d490320f4a20c873"><td class="mdescLeft">&#160;</td><td class="mdescRight">Interrupt Disable Register Offset.  <a href="group__csudma__v1__0.html#ga302a6020f0d9a857d490320f4a20c873">More...</a><br /></td></tr>
<tr class="separator:ga302a6020f0d9a857d490320f4a20c873"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga6072e9b915ebf29b27cddaa7478aade0"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__csudma__v1__0.html#ga6072e9b915ebf29b27cddaa7478aade0">XCSUDMA_I_MASK_OFFSET</a>&#160;&#160;&#160;0x020</td></tr>
<tr class="memdesc:ga6072e9b915ebf29b27cddaa7478aade0"><td class="mdescLeft">&#160;</td><td class="mdescRight">Interrupt Mask Register Offset.  <a href="group__csudma__v1__0.html#ga6072e9b915ebf29b27cddaa7478aade0">More...</a><br /></td></tr>
<tr class="separator:ga6072e9b915ebf29b27cddaa7478aade0"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gabba0bc92253474154042e7eec30f531a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__csudma__v1__0.html#gabba0bc92253474154042e7eec30f531a">XCSUDMA_CTRL2_OFFSET</a>&#160;&#160;&#160;0x024</td></tr>
<tr class="memdesc:gabba0bc92253474154042e7eec30f531a"><td class="mdescLeft">&#160;</td><td class="mdescRight">Interrupt Control Register 2 Offset.  <a href="group__csudma__v1__0.html#gabba0bc92253474154042e7eec30f531a">More...</a><br /></td></tr>
<tr class="separator:gabba0bc92253474154042e7eec30f531a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga4d6c9218a21c89c884ef15a38956469b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__csudma__v1__0.html#ga4d6c9218a21c89c884ef15a38956469b">XCSUDMA_ADDR_MSB_OFFSET</a>&#160;&#160;&#160;0x028</td></tr>
<tr class="memdesc:ga4d6c9218a21c89c884ef15a38956469b"><td class="mdescLeft">&#160;</td><td class="mdescRight">Address's MSB Register Offset.  <a href="group__csudma__v1__0.html#ga4d6c9218a21c89c884ef15a38956469b">More...</a><br /></td></tr>
<tr class="separator:ga4d6c9218a21c89c884ef15a38956469b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga356c14c3ccd1db0253b2db102be41663"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__csudma__v1__0.html#ga356c14c3ccd1db0253b2db102be41663">XCSUDMA_SAFETY_CHK_OFFSET</a>&#160;&#160;&#160;0xFF8</td></tr>
<tr class="memdesc:ga356c14c3ccd1db0253b2db102be41663"><td class="mdescLeft">&#160;</td><td class="mdescRight">Safety Check Field Offset.  <a href="group__csudma__v1__0.html#ga356c14c3ccd1db0253b2db102be41663">More...</a><br /></td></tr>
<tr class="separator:ga356c14c3ccd1db0253b2db102be41663"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga37042539804e77b257be674adb88efa4"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__csudma__v1__0.html#ga37042539804e77b257be674adb88efa4">XCSUDMA_FUTURE_ECO_OFFSET</a>&#160;&#160;&#160;0xFFC</td></tr>
<tr class="memdesc:ga37042539804e77b257be674adb88efa4"><td class="mdescLeft">&#160;</td><td class="mdescRight">Future potential ECO Offset.  <a href="group__csudma__v1__0.html#ga37042539804e77b257be674adb88efa4">More...</a><br /></td></tr>
<tr class="separator:ga37042539804e77b257be674adb88efa4"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">CSU Base address and CSU_DMA reset offset</div></td></tr>
<tr class="memitem:ga9d2d57334cfc09d28c8d3d2db98efa1c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__csudma__v1__0.html#ga9d2d57334cfc09d28c8d3d2db98efa1c">XCSU_BASEADDRESS</a>&#160;&#160;&#160;0xFFCA0000</td></tr>
<tr class="memdesc:ga9d2d57334cfc09d28c8d3d2db98efa1c"><td class="mdescLeft">&#160;</td><td class="mdescRight">CSU Base Address.  <a href="group__csudma__v1__0.html#ga9d2d57334cfc09d28c8d3d2db98efa1c">More...</a><br /></td></tr>
<tr class="separator:ga9d2d57334cfc09d28c8d3d2db98efa1c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga70f2106fc1dd240a5ea17386eb46068d"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__csudma__v1__0.html#ga70f2106fc1dd240a5ea17386eb46068d">XCSU_DMA_RESET_OFFSET</a>&#160;&#160;&#160;0x0000000CU</td></tr>
<tr class="memdesc:ga70f2106fc1dd240a5ea17386eb46068d"><td class="mdescLeft">&#160;</td><td class="mdescRight">CSU_DMA Reset offset.  <a href="group__csudma__v1__0.html#ga70f2106fc1dd240a5ea17386eb46068d">More...</a><br /></td></tr>
<tr class="separator:ga70f2106fc1dd240a5ea17386eb46068d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">CSU_DMA Reset register bit masks</div></td></tr>
<tr class="memitem:ga855c83156a1c7b89b30f1e1dfc23b3fe"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__csudma__v1__0.html#ga855c83156a1c7b89b30f1e1dfc23b3fe">XCSUDMA_RESET_SET_MASK</a>&#160;&#160;&#160;0x00000001U</td></tr>
<tr class="memdesc:ga855c83156a1c7b89b30f1e1dfc23b3fe"><td class="mdescLeft">&#160;</td><td class="mdescRight">Reset set mask.  <a href="group__csudma__v1__0.html#ga855c83156a1c7b89b30f1e1dfc23b3fe">More...</a><br /></td></tr>
<tr class="separator:ga855c83156a1c7b89b30f1e1dfc23b3fe"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gace5f08f560599a1164f9a65cfd1cd75f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__csudma__v1__0.html#gace5f08f560599a1164f9a65cfd1cd75f">XCSUDMA_RESET_UNSET_MASK</a>&#160;&#160;&#160;0x00000000U</td></tr>
<tr class="memdesc:gace5f08f560599a1164f9a65cfd1cd75f"><td class="mdescLeft">&#160;</td><td class="mdescRight">Reset unset mask.  <a href="group__csudma__v1__0.html#gace5f08f560599a1164f9a65cfd1cd75f">More...</a><br /></td></tr>
<tr class="separator:gace5f08f560599a1164f9a65cfd1cd75f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Offset difference for Source and destination</div></td></tr>
<tr class="memitem:ga8605c51a50a0667f6aff787f25aa55ba"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__csudma__v1__0.html#ga8605c51a50a0667f6aff787f25aa55ba">XCSUDMA_OFFSET_DIFF</a>&#160;&#160;&#160;0x00000800U</td></tr>
<tr class="memdesc:ga8605c51a50a0667f6aff787f25aa55ba"><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset difference for source and destination channels.  <a href="group__csudma__v1__0.html#ga8605c51a50a0667f6aff787f25aa55ba">More...</a><br /></td></tr>
<tr class="separator:ga8605c51a50a0667f6aff787f25aa55ba"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Address register bit masks</div></td></tr>
<tr class="memitem:ga23841a10691cb51210298b0614e67573"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__csudma__v1__0.html#ga23841a10691cb51210298b0614e67573">XCSUDMA_ADDR_MASK</a>&#160;&#160;&#160;0xFFFFFFFCU</td></tr>
<tr class="memdesc:ga23841a10691cb51210298b0614e67573"><td class="mdescLeft">&#160;</td><td class="mdescRight">Address mask.  <a href="group__csudma__v1__0.html#ga23841a10691cb51210298b0614e67573">More...</a><br /></td></tr>
<tr class="separator:ga23841a10691cb51210298b0614e67573"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga167f814ecf53fd2228490b5b6d5431df"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__csudma__v1__0.html#ga167f814ecf53fd2228490b5b6d5431df">XCSUDMA_ADDR_LSB_MASK</a>&#160;&#160;&#160;0x00000003U</td></tr>
<tr class="memdesc:ga167f814ecf53fd2228490b5b6d5431df"><td class="mdescLeft">&#160;</td><td class="mdescRight">Address alignment check mask.  <a href="group__csudma__v1__0.html#ga167f814ecf53fd2228490b5b6d5431df">More...</a><br /></td></tr>
<tr class="separator:ga167f814ecf53fd2228490b5b6d5431df"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Size register bit masks and shifts</div></td></tr>
<tr class="memitem:ga2e9db5623d0c9b85088c528d43c9b411"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__csudma__v1__0.html#ga2e9db5623d0c9b85088c528d43c9b411">XCSUDMA_SIZE_MASK</a>&#160;&#160;&#160;0x1FFFFFFCU</td></tr>
<tr class="memdesc:ga2e9db5623d0c9b85088c528d43c9b411"><td class="mdescLeft">&#160;</td><td class="mdescRight">Mask for size.  <a href="group__csudma__v1__0.html#ga2e9db5623d0c9b85088c528d43c9b411">More...</a><br /></td></tr>
<tr class="separator:ga2e9db5623d0c9b85088c528d43c9b411"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaf0a5114bb4e675c0e9d933a2d235ac6f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__csudma__v1__0.html#gaf0a5114bb4e675c0e9d933a2d235ac6f">XCSUDMA_LAST_WORD_MASK</a>&#160;&#160;&#160;0x00000001U</td></tr>
<tr class="memdesc:gaf0a5114bb4e675c0e9d933a2d235ac6f"><td class="mdescLeft">&#160;</td><td class="mdescRight">Last word check bit mask.  <a href="group__csudma__v1__0.html#gaf0a5114bb4e675c0e9d933a2d235ac6f">More...</a><br /></td></tr>
<tr class="separator:gaf0a5114bb4e675c0e9d933a2d235ac6f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gae1d5689d4fbd05c2e7f6b2a34bcbfb09"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__csudma__v1__0.html#gae1d5689d4fbd05c2e7f6b2a34bcbfb09">XCSUDMA_SIZE_SHIFT</a>&#160;&#160;&#160;2U</td></tr>
<tr class="memdesc:gae1d5689d4fbd05c2e7f6b2a34bcbfb09"><td class="mdescLeft">&#160;</td><td class="mdescRight">Shift for size.  <a href="group__csudma__v1__0.html#gae1d5689d4fbd05c2e7f6b2a34bcbfb09">More...</a><br /></td></tr>
<tr class="separator:gae1d5689d4fbd05c2e7f6b2a34bcbfb09"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Status register bit masks and shifts</div></td></tr>
<tr class="memitem:gaf3e6ebc15a10616414fe7f5f089f6086"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__csudma__v1__0.html#gaf3e6ebc15a10616414fe7f5f089f6086">XCSUDMA_STS_DONE_CNT_MASK</a>&#160;&#160;&#160;0x0000E000U</td></tr>
<tr class="memdesc:gaf3e6ebc15a10616414fe7f5f089f6086"><td class="mdescLeft">&#160;</td><td class="mdescRight">Count done mask.  <a href="group__csudma__v1__0.html#gaf3e6ebc15a10616414fe7f5f089f6086">More...</a><br /></td></tr>
<tr class="separator:gaf3e6ebc15a10616414fe7f5f089f6086"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gad60406d26eb204edbea24190a400a1f5"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__csudma__v1__0.html#gad60406d26eb204edbea24190a400a1f5">XCSUDMA_STS_FIFO_LEVEL_MASK</a>&#160;&#160;&#160;0x00001FE0U</td></tr>
<tr class="memdesc:gad60406d26eb204edbea24190a400a1f5"><td class="mdescLeft">&#160;</td><td class="mdescRight">FIFO level mask.  <a href="group__csudma__v1__0.html#gad60406d26eb204edbea24190a400a1f5">More...</a><br /></td></tr>
<tr class="separator:gad60406d26eb204edbea24190a400a1f5"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga56a8b1f3c33817adbe8a131a227a4564"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__csudma__v1__0.html#ga56a8b1f3c33817adbe8a131a227a4564">XCUSDMA_STS_OUTSTDG_MASK</a>&#160;&#160;&#160;0x0000001EU</td></tr>
<tr class="memdesc:ga56a8b1f3c33817adbe8a131a227a4564"><td class="mdescLeft">&#160;</td><td class="mdescRight">No.of outstanding read/write commands mask.  <a href="group__csudma__v1__0.html#ga56a8b1f3c33817adbe8a131a227a4564">More...</a><br /></td></tr>
<tr class="separator:ga56a8b1f3c33817adbe8a131a227a4564"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga446c26de02f645feea8f4d38a432ef67"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__csudma__v1__0.html#ga446c26de02f645feea8f4d38a432ef67">XCSUDMA_STS_BUSY_MASK</a>&#160;&#160;&#160;0x00000001U</td></tr>
<tr class="memdesc:ga446c26de02f645feea8f4d38a432ef67"><td class="mdescLeft">&#160;</td><td class="mdescRight">Busy mask.  <a href="group__csudma__v1__0.html#ga446c26de02f645feea8f4d38a432ef67">More...</a><br /></td></tr>
<tr class="separator:ga446c26de02f645feea8f4d38a432ef67"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gabe346c87e4cb91d915c4fe93780fe292"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__csudma__v1__0.html#gabe346c87e4cb91d915c4fe93780fe292">XCSUDMA_STS_DONE_CNT_SHIFT</a>&#160;&#160;&#160;13U</td></tr>
<tr class="memdesc:gabe346c87e4cb91d915c4fe93780fe292"><td class="mdescLeft">&#160;</td><td class="mdescRight">Shift for Count done.  <a href="group__csudma__v1__0.html#gabe346c87e4cb91d915c4fe93780fe292">More...</a><br /></td></tr>
<tr class="separator:gabe346c87e4cb91d915c4fe93780fe292"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga15463a130472a0432626f963bc2ce7d3"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__csudma__v1__0.html#ga15463a130472a0432626f963bc2ce7d3">XCSUDMA_STS_FIFO_LEVEL_SHIFT</a>&#160;&#160;&#160;5U</td></tr>
<tr class="memdesc:ga15463a130472a0432626f963bc2ce7d3"><td class="mdescLeft">&#160;</td><td class="mdescRight">Shift for FIFO level.  <a href="group__csudma__v1__0.html#ga15463a130472a0432626f963bc2ce7d3">More...</a><br /></td></tr>
<tr class="separator:ga15463a130472a0432626f963bc2ce7d3"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gad6719cf8d08f8710300ce922f6e52e40"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__csudma__v1__0.html#gad6719cf8d08f8710300ce922f6e52e40">XCUSDMA_STS_OUTSTDG_SHIFT</a>&#160;&#160;&#160;1U</td></tr>
<tr class="memdesc:gad6719cf8d08f8710300ce922f6e52e40"><td class="mdescLeft">&#160;</td><td class="mdescRight">Shift for No.of outstanding read/write commands.  <a href="group__csudma__v1__0.html#gad6719cf8d08f8710300ce922f6e52e40">More...</a><br /></td></tr>
<tr class="separator:gad6719cf8d08f8710300ce922f6e52e40"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Control register bit masks and shifts</div></td></tr>
<tr class="memitem:ga1d0f942367f084568b2adfb2b074443a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__csudma__v1__0.html#ga1d0f942367f084568b2adfb2b074443a">XCSUDMA_CTRL_SSS_FIFOTHRESH_MASK</a>&#160;&#160;&#160;0xFE000000U</td></tr>
<tr class="memdesc:ga1d0f942367f084568b2adfb2b074443a"><td class="mdescLeft">&#160;</td><td class="mdescRight">SSS FIFO threshold value mask.  <a href="group__csudma__v1__0.html#ga1d0f942367f084568b2adfb2b074443a">More...</a><br /></td></tr>
<tr class="separator:ga1d0f942367f084568b2adfb2b074443a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga0e6766f31a6332796f3b8ff912c786e5"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__csudma__v1__0.html#ga0e6766f31a6332796f3b8ff912c786e5">XCSUDMA_CTRL_APB_ERR_MASK</a>&#160;&#160;&#160;0x01000000U</td></tr>
<tr class="memdesc:ga0e6766f31a6332796f3b8ff912c786e5"><td class="mdescLeft">&#160;</td><td class="mdescRight">APB register access error mask.  <a href="group__csudma__v1__0.html#ga0e6766f31a6332796f3b8ff912c786e5">More...</a><br /></td></tr>
<tr class="separator:ga0e6766f31a6332796f3b8ff912c786e5"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gad5e388818030cd2ca04d9dc867440329"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__csudma__v1__0.html#gad5e388818030cd2ca04d9dc867440329">XCSUDMA_CTRL_ENDIAN_MASK</a>&#160;&#160;&#160;0x00800000U</td></tr>
<tr class="memdesc:gad5e388818030cd2ca04d9dc867440329"><td class="mdescLeft">&#160;</td><td class="mdescRight">Endianess mask.  <a href="group__csudma__v1__0.html#gad5e388818030cd2ca04d9dc867440329">More...</a><br /></td></tr>
<tr class="separator:gad5e388818030cd2ca04d9dc867440329"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gae3c25e9c83a1e84d061746fa01142305"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__csudma__v1__0.html#gae3c25e9c83a1e84d061746fa01142305">XCSUDMA_CTRL_BURST_MASK</a>&#160;&#160;&#160;0x00400000U</td></tr>
<tr class="memdesc:gae3c25e9c83a1e84d061746fa01142305"><td class="mdescLeft">&#160;</td><td class="mdescRight">AXI burst type mask.  <a href="group__csudma__v1__0.html#gae3c25e9c83a1e84d061746fa01142305">More...</a><br /></td></tr>
<tr class="separator:gae3c25e9c83a1e84d061746fa01142305"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga8f46672097f2d6533df165bbc7bdf0e6"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__csudma__v1__0.html#ga8f46672097f2d6533df165bbc7bdf0e6">XCSUDMA_CTRL_TIMEOUT_MASK</a>&#160;&#160;&#160;0x003FFC00U</td></tr>
<tr class="memdesc:ga8f46672097f2d6533df165bbc7bdf0e6"><td class="mdescLeft">&#160;</td><td class="mdescRight">Time out value mask.  <a href="group__csudma__v1__0.html#ga8f46672097f2d6533df165bbc7bdf0e6">More...</a><br /></td></tr>
<tr class="separator:ga8f46672097f2d6533df165bbc7bdf0e6"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga083616ad7e4d22a9abfd3ab959c1eae4"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__csudma__v1__0.html#ga083616ad7e4d22a9abfd3ab959c1eae4">XCSUDMA_CTRL_FIFO_THRESH_MASK</a>&#160;&#160;&#160;0x000003FCU</td></tr>
<tr class="memdesc:ga083616ad7e4d22a9abfd3ab959c1eae4"><td class="mdescLeft">&#160;</td><td class="mdescRight">FIFO threshold mask.  <a href="group__csudma__v1__0.html#ga083616ad7e4d22a9abfd3ab959c1eae4">More...</a><br /></td></tr>
<tr class="separator:ga083616ad7e4d22a9abfd3ab959c1eae4"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga8bbf92fafd6d0808e8db4a6b772e5b6f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__csudma__v1__0.html#ga8bbf92fafd6d0808e8db4a6b772e5b6f">XCSUDMA_CTRL_PAUSE_MEM_MASK</a>&#160;&#160;&#160;0x00000001U</td></tr>
<tr class="memdesc:ga8bbf92fafd6d0808e8db4a6b772e5b6f"><td class="mdescLeft">&#160;</td><td class="mdescRight">Memory pause mask.  <a href="group__csudma__v1__0.html#ga8bbf92fafd6d0808e8db4a6b772e5b6f">More...</a><br /></td></tr>
<tr class="separator:ga8bbf92fafd6d0808e8db4a6b772e5b6f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gacdb2f8a8d2b8f782ffec216f6870c0a8"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__csudma__v1__0.html#gacdb2f8a8d2b8f782ffec216f6870c0a8">XCSUDMA_CTRL_PAUSE_STRM_MASK</a>&#160;&#160;&#160;0x00000002U</td></tr>
<tr class="memdesc:gacdb2f8a8d2b8f782ffec216f6870c0a8"><td class="mdescLeft">&#160;</td><td class="mdescRight">Stream pause mask.  <a href="group__csudma__v1__0.html#gacdb2f8a8d2b8f782ffec216f6870c0a8">More...</a><br /></td></tr>
<tr class="separator:gacdb2f8a8d2b8f782ffec216f6870c0a8"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaba325b1173d26c916097badcff6ab3d5"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__csudma__v1__0.html#gaba325b1173d26c916097badcff6ab3d5">XCSUDMA_CTRL_SSS_FIFOTHRESH_SHIFT</a>&#160;&#160;&#160;25U</td></tr>
<tr class="memdesc:gaba325b1173d26c916097badcff6ab3d5"><td class="mdescLeft">&#160;</td><td class="mdescRight">SSS FIFO threshold shift.  <a href="group__csudma__v1__0.html#gaba325b1173d26c916097badcff6ab3d5">More...</a><br /></td></tr>
<tr class="separator:gaba325b1173d26c916097badcff6ab3d5"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gae7479f63823b9eb5f36139fd7414e56a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__csudma__v1__0.html#gae7479f63823b9eb5f36139fd7414e56a">XCSUDMA_CTRL_APB_ERR_SHIFT</a>&#160;&#160;&#160;24U</td></tr>
<tr class="memdesc:gae7479f63823b9eb5f36139fd7414e56a"><td class="mdescLeft">&#160;</td><td class="mdescRight">APB error shift.  <a href="group__csudma__v1__0.html#gae7479f63823b9eb5f36139fd7414e56a">More...</a><br /></td></tr>
<tr class="separator:gae7479f63823b9eb5f36139fd7414e56a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga19e7f9c690bdf3c1633ea60845ca1285"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__csudma__v1__0.html#ga19e7f9c690bdf3c1633ea60845ca1285">XCSUDMA_CTRL_ENDIAN_SHIFT</a>&#160;&#160;&#160;23U</td></tr>
<tr class="memdesc:ga19e7f9c690bdf3c1633ea60845ca1285"><td class="mdescLeft">&#160;</td><td class="mdescRight">Endianess shift.  <a href="group__csudma__v1__0.html#ga19e7f9c690bdf3c1633ea60845ca1285">More...</a><br /></td></tr>
<tr class="separator:ga19e7f9c690bdf3c1633ea60845ca1285"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaf44a7c00dd4ffbd3405b66a8fac60860"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__csudma__v1__0.html#gaf44a7c00dd4ffbd3405b66a8fac60860">XCSUDMA_CTRL_BURST_SHIFT</a>&#160;&#160;&#160;22U</td></tr>
<tr class="memdesc:gaf44a7c00dd4ffbd3405b66a8fac60860"><td class="mdescLeft">&#160;</td><td class="mdescRight">AXI burst type shift.  <a href="group__csudma__v1__0.html#gaf44a7c00dd4ffbd3405b66a8fac60860">More...</a><br /></td></tr>
<tr class="separator:gaf44a7c00dd4ffbd3405b66a8fac60860"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga0084f3cdeacc4098f70521b50006025d"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__csudma__v1__0.html#ga0084f3cdeacc4098f70521b50006025d">XCSUDMA_CTRL_TIMEOUT_SHIFT</a>&#160;&#160;&#160;10U</td></tr>
<tr class="memdesc:ga0084f3cdeacc4098f70521b50006025d"><td class="mdescLeft">&#160;</td><td class="mdescRight">Time out value shift.  <a href="group__csudma__v1__0.html#ga0084f3cdeacc4098f70521b50006025d">More...</a><br /></td></tr>
<tr class="separator:ga0084f3cdeacc4098f70521b50006025d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga0ebe79007915c3f88a41b75168fbe8ff"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__csudma__v1__0.html#ga0ebe79007915c3f88a41b75168fbe8ff">XCSUDMA_CTRL_FIFO_THRESH_SHIFT</a>&#160;&#160;&#160;2U</td></tr>
<tr class="memdesc:ga0ebe79007915c3f88a41b75168fbe8ff"><td class="mdescLeft">&#160;</td><td class="mdescRight">FIFO thresh shift.  <a href="group__csudma__v1__0.html#ga0ebe79007915c3f88a41b75168fbe8ff">More...</a><br /></td></tr>
<tr class="separator:ga0ebe79007915c3f88a41b75168fbe8ff"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">CheckSum register bit masks</div></td></tr>
<tr class="memitem:ga94f131f080543e47020a2fd4d5d4cf7f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__csudma__v1__0.html#ga94f131f080543e47020a2fd4d5d4cf7f">XCSUDMA_CRC_RESET_MASK</a>&#160;&#160;&#160;0x00000000U</td></tr>
<tr class="memdesc:ga94f131f080543e47020a2fd4d5d4cf7f"><td class="mdescLeft">&#160;</td><td class="mdescRight">Mask to reset value of check sum.  <a href="group__csudma__v1__0.html#ga94f131f080543e47020a2fd4d5d4cf7f">More...</a><br /></td></tr>
<tr class="separator:ga94f131f080543e47020a2fd4d5d4cf7f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">Interrupt Enable/Disable/Mask/Status registers bit masks</div></td></tr>
<tr class="memitem:ga33dc1a1076170c9ca47df1c3451bdfe5"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__csudma__v1__0.html#ga33dc1a1076170c9ca47df1c3451bdfe5">XCSUDMA_IXR_FIFO_OVERFLOW_MASK</a>&#160;&#160;&#160;0x00000001U</td></tr>
<tr class="memdesc:ga33dc1a1076170c9ca47df1c3451bdfe5"><td class="mdescLeft">&#160;</td><td class="mdescRight">FIFO overflow mask, it is valid only to Destination Channel.  <a href="group__csudma__v1__0.html#ga33dc1a1076170c9ca47df1c3451bdfe5">More...</a><br /></td></tr>
<tr class="separator:ga33dc1a1076170c9ca47df1c3451bdfe5"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga6e7d15f2dfaa7afef685f382db12c62e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__csudma__v1__0.html#ga6e7d15f2dfaa7afef685f382db12c62e">XCSUDMA_IXR_INVALID_APB_MASK</a>&#160;&#160;&#160;0x00000040U</td></tr>
<tr class="memdesc:ga6e7d15f2dfaa7afef685f382db12c62e"><td class="mdescLeft">&#160;</td><td class="mdescRight">Invalid APB access mask.  <a href="group__csudma__v1__0.html#ga6e7d15f2dfaa7afef685f382db12c62e">More...</a><br /></td></tr>
<tr class="separator:ga6e7d15f2dfaa7afef685f382db12c62e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaf727ccf4d9bbbce46d61f67be041b40c"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__csudma__v1__0.html#gaf727ccf4d9bbbce46d61f67be041b40c">XCSUDMA_IXR_FIFO_THRESHHIT_MASK</a>&#160;&#160;&#160;0x00000020U</td></tr>
<tr class="memdesc:gaf727ccf4d9bbbce46d61f67be041b40c"><td class="mdescLeft">&#160;</td><td class="mdescRight">FIFO threshold hit indicator mask.  <a href="group__csudma__v1__0.html#gaf727ccf4d9bbbce46d61f67be041b40c">More...</a><br /></td></tr>
<tr class="separator:gaf727ccf4d9bbbce46d61f67be041b40c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gadb917cad64699bd0fc6e21c1fec74068"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__csudma__v1__0.html#gadb917cad64699bd0fc6e21c1fec74068">XCSUDMA_IXR_TIMEOUT_MEM_MASK</a>&#160;&#160;&#160;0x00000010U</td></tr>
<tr class="memdesc:gadb917cad64699bd0fc6e21c1fec74068"><td class="mdescLeft">&#160;</td><td class="mdescRight">Time out counter expired to access memory mask.  <a href="group__csudma__v1__0.html#gadb917cad64699bd0fc6e21c1fec74068">More...</a><br /></td></tr>
<tr class="separator:gadb917cad64699bd0fc6e21c1fec74068"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga7fc13f5152cf0098d76d4b78b08702e8"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__csudma__v1__0.html#ga7fc13f5152cf0098d76d4b78b08702e8">XCSUDMA_IXR_TIMEOUT_STRM_MASK</a>&#160;&#160;&#160;0x00000008U</td></tr>
<tr class="memdesc:ga7fc13f5152cf0098d76d4b78b08702e8"><td class="mdescLeft">&#160;</td><td class="mdescRight">Time out counter expired to access stream mask.  <a href="group__csudma__v1__0.html#ga7fc13f5152cf0098d76d4b78b08702e8">More...</a><br /></td></tr>
<tr class="separator:ga7fc13f5152cf0098d76d4b78b08702e8"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gac6e2bc9f25b7160249710c395a74d933"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__csudma__v1__0.html#gac6e2bc9f25b7160249710c395a74d933">XCSUDMA_IXR_AXI_WRERR_MASK</a>&#160;&#160;&#160;0x00000004U</td></tr>
<tr class="memdesc:gac6e2bc9f25b7160249710c395a74d933"><td class="mdescLeft">&#160;</td><td class="mdescRight">AXI Read/Write error mask.  <a href="group__csudma__v1__0.html#gac6e2bc9f25b7160249710c395a74d933">More...</a><br /></td></tr>
<tr class="separator:gac6e2bc9f25b7160249710c395a74d933"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga0dbd333c70de601e769b8542552eb7e4"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__csudma__v1__0.html#ga0dbd333c70de601e769b8542552eb7e4">XCSUDMA_IXR_DONE_MASK</a>&#160;&#160;&#160;0x00000002U</td></tr>
<tr class="memdesc:ga0dbd333c70de601e769b8542552eb7e4"><td class="mdescLeft">&#160;</td><td class="mdescRight">Done mask.  <a href="group__csudma__v1__0.html#ga0dbd333c70de601e769b8542552eb7e4">More...</a><br /></td></tr>
<tr class="separator:ga0dbd333c70de601e769b8542552eb7e4"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga670d9fac28bd9de6b6f6abcb5fda64cc"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__csudma__v1__0.html#ga670d9fac28bd9de6b6f6abcb5fda64cc">XCSUDMA_IXR_MEM_DONE_MASK</a>&#160;&#160;&#160;0x00000001U</td></tr>
<tr class="memdesc:ga670d9fac28bd9de6b6f6abcb5fda64cc"><td class="mdescLeft">&#160;</td><td class="mdescRight">Memory done mask, it is valid only for source channel.  <a href="group__csudma__v1__0.html#ga670d9fac28bd9de6b6f6abcb5fda64cc">More...</a><br /></td></tr>
<tr class="separator:ga670d9fac28bd9de6b6f6abcb5fda64cc"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga441edc2ec9eadb8093ac0ab41e0162d2"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__csudma__v1__0.html#ga441edc2ec9eadb8093ac0ab41e0162d2">XCSUDMA_IXR_SRC_MASK</a>&#160;&#160;&#160;0x0000007FU</td></tr>
<tr class="memdesc:ga441edc2ec9eadb8093ac0ab41e0162d2"><td class="mdescLeft">&#160;</td><td class="mdescRight">((XCSUDMA_IXR_INVALID_APB_MASK)| (XCSUDMA_IXR_FIFO_THRESHHIT_MASK) | (XCSUDMA_IXR_TIMEOUT_MEM_MASK) | (XCSUDMA_IXR_TIMEOUT_STRM_MASK) | (XCSUDMA_IXR_AXI_WRERR_MASK) | (XCSUDMA_IXR_DONE_MASK) | (XCSUDMA_IXR_MEM_DONE_MASK))  <a href="group__csudma__v1__0.html#ga441edc2ec9eadb8093ac0ab41e0162d2">More...</a><br /></td></tr>
<tr class="separator:ga441edc2ec9eadb8093ac0ab41e0162d2"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gadfb7ef2922c9ceb4804bc87620c35134"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__csudma__v1__0.html#gadfb7ef2922c9ceb4804bc87620c35134">XCSUDMA_IXR_DST_MASK</a>&#160;&#160;&#160;0x000000FEU</td></tr>
<tr class="memdesc:gadfb7ef2922c9ceb4804bc87620c35134"><td class="mdescLeft">&#160;</td><td class="mdescRight">((XCSUDMA_IXR_FIFO_OVERFLOW_MASK) | (XCSUDMA_IXR_INVALID_APB_MASK) | (XCSUDMA_IXR_FIFO_THRESHHIT_MASK) | (XCSUDMA_IXR_TIMEOUT_MEM_MASK) | (XCSUDMA_IXR_TIMEOUT_STRM_MASK) | (XCSUDMA_IXR_AXI_WRERR_MASK) | (XCSUDMA_IXR_DONE_MASK))  <a href="group__csudma__v1__0.html#gadfb7ef2922c9ceb4804bc87620c35134">More...</a><br /></td></tr>
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<tr><td colspan="2"><div class="groupHeader">Control register 2 bit masks and shifts</div></td></tr>
<tr class="memitem:ga2994ec3a4ddd8feadffbdeafa27fdd8a"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__csudma__v1__0.html#ga2994ec3a4ddd8feadffbdeafa27fdd8a">XCSUDMA_CTRL2_RESERVED_MASK</a>&#160;&#160;&#160;0x083F0000U</td></tr>
<tr class="memdesc:ga2994ec3a4ddd8feadffbdeafa27fdd8a"><td class="mdescLeft">&#160;</td><td class="mdescRight">Reserved bits mask.  <a href="group__csudma__v1__0.html#ga2994ec3a4ddd8feadffbdeafa27fdd8a">More...</a><br /></td></tr>
<tr class="separator:ga2994ec3a4ddd8feadffbdeafa27fdd8a"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga668128c78f38748fb04d519246453033"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__csudma__v1__0.html#ga668128c78f38748fb04d519246453033">XCSUDMA_CTRL2_ACACHE_MASK</a>&#160;&#160;&#160;0X07000000U</td></tr>
<tr class="memdesc:ga668128c78f38748fb04d519246453033"><td class="mdescLeft">&#160;</td><td class="mdescRight">AXI CACHE mask.  <a href="group__csudma__v1__0.html#ga668128c78f38748fb04d519246453033">More...</a><br /></td></tr>
<tr class="separator:ga668128c78f38748fb04d519246453033"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gac388240ecd8b78fe7a9051eb065e1d00"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__csudma__v1__0.html#gac388240ecd8b78fe7a9051eb065e1d00">XCSUDMA_CTRL2_ROUTE_MASK</a>&#160;&#160;&#160;0x00800000U</td></tr>
<tr class="memdesc:gac388240ecd8b78fe7a9051eb065e1d00"><td class="mdescLeft">&#160;</td><td class="mdescRight">Route mask.  <a href="group__csudma__v1__0.html#gac388240ecd8b78fe7a9051eb065e1d00">More...</a><br /></td></tr>
<tr class="separator:gac388240ecd8b78fe7a9051eb065e1d00"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gad9d80f9c720cd3539b8086c467038432"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__csudma__v1__0.html#gad9d80f9c720cd3539b8086c467038432">XCSUDMA_CTRL2_TIMEOUT_EN_MASK</a>&#160;&#160;&#160;0x00400000U</td></tr>
<tr class="memdesc:gad9d80f9c720cd3539b8086c467038432"><td class="mdescLeft">&#160;</td><td class="mdescRight">Time out counters enable mask.  <a href="group__csudma__v1__0.html#gad9d80f9c720cd3539b8086c467038432">More...</a><br /></td></tr>
<tr class="separator:gad9d80f9c720cd3539b8086c467038432"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga9bc4b8e583b6c947023490e817352340"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__csudma__v1__0.html#ga9bc4b8e583b6c947023490e817352340">XCSUDMA_CTRL2_TIMEOUT_PRE_MASK</a>&#160;&#160;&#160;0x0000FFF0U</td></tr>
<tr class="memdesc:ga9bc4b8e583b6c947023490e817352340"><td class="mdescLeft">&#160;</td><td class="mdescRight">Time out pre mask.  <a href="group__csudma__v1__0.html#ga9bc4b8e583b6c947023490e817352340">More...</a><br /></td></tr>
<tr class="separator:ga9bc4b8e583b6c947023490e817352340"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga56c33f23233637055b848282bbb29cb6"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__csudma__v1__0.html#ga56c33f23233637055b848282bbb29cb6">XCSUDMA_CTRL2_MAXCMDS_MASK</a>&#160;&#160;&#160;0x0000000FU</td></tr>
<tr class="memdesc:ga56c33f23233637055b848282bbb29cb6"><td class="mdescLeft">&#160;</td><td class="mdescRight">Maximum commands mask.  <a href="group__csudma__v1__0.html#ga56c33f23233637055b848282bbb29cb6">More...</a><br /></td></tr>
<tr class="separator:ga56c33f23233637055b848282bbb29cb6"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gadfeec3d6cc61726efa5b38c5465bfe22"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__csudma__v1__0.html#gadfeec3d6cc61726efa5b38c5465bfe22">XCSUDMA_CTRL2_RESET_MASK</a>&#160;&#160;&#160;0x0000FFF8U</td></tr>
<tr class="memdesc:gadfeec3d6cc61726efa5b38c5465bfe22"><td class="mdescLeft">&#160;</td><td class="mdescRight">Reset mask.  <a href="group__csudma__v1__0.html#gadfeec3d6cc61726efa5b38c5465bfe22">More...</a><br /></td></tr>
<tr class="separator:gadfeec3d6cc61726efa5b38c5465bfe22"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gab682491284b66d39496860a8333951c7"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__csudma__v1__0.html#gab682491284b66d39496860a8333951c7">XCSUDMA_CTRL2_ACACHE_SHIFT</a>&#160;&#160;&#160;24U</td></tr>
<tr class="memdesc:gab682491284b66d39496860a8333951c7"><td class="mdescLeft">&#160;</td><td class="mdescRight">Shift for AXI R/W CACHE.  <a href="group__csudma__v1__0.html#gab682491284b66d39496860a8333951c7">More...</a><br /></td></tr>
<tr class="separator:gab682491284b66d39496860a8333951c7"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaba47338630b6e8aaa756aa442e886bc0"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__csudma__v1__0.html#gaba47338630b6e8aaa756aa442e886bc0">XCSUDMA_CTRL2_ROUTE_SHIFT</a>&#160;&#160;&#160;23U</td></tr>
<tr class="memdesc:gaba47338630b6e8aaa756aa442e886bc0"><td class="mdescLeft">&#160;</td><td class="mdescRight">Shift for route.  <a href="group__csudma__v1__0.html#gaba47338630b6e8aaa756aa442e886bc0">More...</a><br /></td></tr>
<tr class="separator:gaba47338630b6e8aaa756aa442e886bc0"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gad4d0b2a2d8b593ac49f879567fd2f076"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__csudma__v1__0.html#gad4d0b2a2d8b593ac49f879567fd2f076">XCSUDMA_CTRL2_TIMEOUT_EN_SHIFT</a>&#160;&#160;&#160;22U</td></tr>
<tr class="memdesc:gad4d0b2a2d8b593ac49f879567fd2f076"><td class="mdescLeft">&#160;</td><td class="mdescRight">Shift for Timeout enable feild.  <a href="group__csudma__v1__0.html#gad4d0b2a2d8b593ac49f879567fd2f076">More...</a><br /></td></tr>
<tr class="separator:gad4d0b2a2d8b593ac49f879567fd2f076"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gad1b3913111c69b6bd2be606dbe341ab4"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__csudma__v1__0.html#gad1b3913111c69b6bd2be606dbe341ab4">XCSUDMA_CTRL2_TIMEOUT_PRE_SHIFT</a>&#160;&#160;&#160;4U</td></tr>
<tr class="memdesc:gad1b3913111c69b6bd2be606dbe341ab4"><td class="mdescLeft">&#160;</td><td class="mdescRight">Shift for Timeout pre feild.  <a href="group__csudma__v1__0.html#gad1b3913111c69b6bd2be606dbe341ab4">More...</a><br /></td></tr>
<tr class="separator:gad1b3913111c69b6bd2be606dbe341ab4"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr><td colspan="2"><div class="groupHeader">MSB Address register bit masks and shifts</div></td></tr>
<tr class="memitem:ga29841329ffd65ef1b49870b89171188d"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__csudma__v1__0.html#ga29841329ffd65ef1b49870b89171188d">XCSUDMA_MSB_ADDR_MASK</a>&#160;&#160;&#160;0x0001FFFFU</td></tr>
<tr class="memdesc:ga29841329ffd65ef1b49870b89171188d"><td class="mdescLeft">&#160;</td><td class="mdescRight">MSB bits of address mask.  <a href="group__csudma__v1__0.html#ga29841329ffd65ef1b49870b89171188d">More...</a><br /></td></tr>
<tr class="separator:ga29841329ffd65ef1b49870b89171188d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga8cb51c5b9c07f84acf19defd57ae764b"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__csudma__v1__0.html#ga8cb51c5b9c07f84acf19defd57ae764b">XCSUDMA_MSB_ADDR_SHIFT</a>&#160;&#160;&#160;32U</td></tr>
<tr class="memdesc:ga8cb51c5b9c07f84acf19defd57ae764b"><td class="mdescLeft">&#160;</td><td class="mdescRight">Shift for MSB bits of address.  <a href="group__csudma__v1__0.html#ga8cb51c5b9c07f84acf19defd57ae764b">More...</a><br /></td></tr>
<tr class="separator:ga8cb51c5b9c07f84acf19defd57ae764b"><td class="memSeparator" colspan="2">&#160;</td></tr>
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